1. Field of the Invention
The present invention relates to a semiconductor device including a trench gate structure typified by a vertical field effect transistor, and specifically relates to a semiconductor device provided with a structure suitable for increasing a turn off capability or latch-up immunity.
2. Description of the Related Art
For higher electric power in power semiconductor devices, there has been an increasing demand for reduction in loss and increase in current capacity of elements, recently.
To reduce the loss of the elements, it is important to reduce an on-voltage, and trench insulated gate bipolar transistors (hereinafter, referred to as trench IGBTs), which are vertical field effect transistors advantageous in low on-voltage characteristics, is often used. To increase the current capacity of elements, it is required to increase chip size, and chips with a size of not less than 1 cm square are used.
However, when the chip size is increased, there is a problem that gate resistance is increased because a trench IGBT cell is distanced from a gate terminal lead section and the switching loss is increased.
Therefore, the trench IGBT cell is divided into a plurality of cells, and gate wiring sections are provided on peripheries of the divided trench IGBT cells as well as on the periphery of the chip to reduce the gate resistance.
In the trench IGBT, a trench pattern is formed in a semiconductor layer, and a gate electrode is embedded in the trench pattern with a gate insulating film interposed therebetween. For the trench pattern, a stripe structure in which a plurality of parallel trench lines are formed has hitherto been often used.
In the trench pattern of this stripe structure, both ends of each trench line are unconnected, so that dislocations caused by oxidation-induced stress tend to be generated in the vicinity of each end.
As shown in Japanese Patent Laid-Open Publication [KOKAI] Hei 10-256545, there has been known a semiconductor device including a trench pattern to solve this problem.
A description will be given of a trench pattern of a semiconductor device disclosed in the Publication with reference to FIG. 4. FIG. 4 is a conceptual view showing a main portion of the semiconductor device.
As shown in the drawing, an end 102a of a trench line 101a is bifurcated and integrally connected to ends 102b and 102c of trench lines 101b and 101c adjacent to both sides of the trench line 101a with connecting portions 103a and 103b interposed therebetween, respectively. Accordingly, a viscous flow of the gate insulating film is not blocked, therefore the oxidation-induced stress is reduced and the generation of dislocations is suppressed.
FIGS. 5A and 5B are views showing an example of the trench IGBT using the trench pattern disclosed in the Publication. FIG. 5A is a plan view showing two trench IGBT cells horizontally separated, and FIG. 5B is a cross-sectional view taken along a line C—C of FIG. 5A and viewed in a direction of an arrow. Electrode wires not shown in FIG. 5A are shown in FIG. 5B.
As shown in the drawings, an end 112a of a trench line 111 is integrally connected to ends 112b and 112c of trench lines adjacent to the both sides of the trench line 111 with connecting portions 113a and 113b interposed therebetween, respectively.
However, a trench IGBT 115 composed of trench IGBT cells 114a and 114b, each having the trench pattern disclosed in the Publication, has a problem. When the trench IGBT 115 is turned on, holes injected into an n-type layer 117 through a P+ type semiconductor substrate 116 are accumulated in a region directly under a gate wire 118 sandwiched between the adjacent trench IGBT cells 114a and 114b. When the trench IGBT 115 is turned off, the accumulated holes remain to cause malfunction of the trench IGBT 115.
These accumulated holes should be discharged through emitter electrodes 119a and 119b of the nearest trench IGBT cells. However, current paths between the emitter electrodes 119a and 119b and the region directly under the gate wire 118, in which the holes are accumulated, are divided by trenches 120a and 120b, therefore holes are difficult to be discharged.
Therefore, the holes remaining in the region directly under the gate wire 118 activates an NPN transistor (NPN transistor formed of an N+ type emitter layer 121, a P type base layer 122, and an N− type layer 117) in the vicinity thereof to cause malfunction of the trench IGBT 115.
Accordingly, in the IGBT with the trench pattern disclosed in the Publication, in which the end of a trench line is connected to the ends of the trench lines adjacent to both sides thereof, the latch-up immunity is lowered, and elements could be broken. Therefore, increasing the current capacity is difficult.
In the aforementioned IGBT with the stripe trench pattern, high gate voltage withstand capability cannot be obtained. On the other hand, the IGBT with the trench pattern disclosed in the Publication has the problem with the latch-up immunity. In other words, it has been difficult that the conventional trench IGBT satisfies both the gate voltage withstand capability and the latch-up immunity when the chip size is increased.